Cyclic redundancy checking (“CRC”) is a well-known, conventional technique for finding data transmission errors. Typically, CRC is performed “on-the-fly” by hardware or logic circuitry, usually on serial data received in a device or system. Cyclic redundancy code (a result of a CRC determination) is typically generated at the data source, and is typically included in the header of a data packet or frame.
As shown in FIG. 1A, one type of data packet 10 comprises a plurality of words Data0 12 through DataN 20, where N is an integer of any length conforming to a conventional network data communications protocol. Each data word Data0-DataN contains 32 bits of data, consistent with the art-recognized meaning of “word” as it applies to data transmissions. To ensure that data packet 10 was transmitted successfully (i.e., without errors), a CRC calculation may be performed on the data therein. Data packet 10 may further comprise non-data information, such as a header and/or trailer of fixed or variable length, depending on the network and/or system. However, since headers and trailers are not data, they are not included in a CRC determination.
Since data packet 10 contains data words 12-20 each having the same length, a single CRC circuit block can perform the CRC calculation. FIG. 1B shows conventional receiver circuit blocks configured to process incoming data and perform a CRC calculation. For example, receiver block RX 52 receives serial data from a source device in a network. Such data is typically binary or digital data. Receiver block RX 52 is generally configured to recover a clock signal from the incoming serial data packet 10, and may be further configured to deserialize the packet (i.e., convert the serial data bits to parallel data bits). Header detection and removal block 54 receives the data packet 10 from receiver block 52 on serial or parallel bus 56, and detects and removes non-data information (such as a header) from the packet. The data words Data0 12 through DataN 20 are transmitted to CRC block 60 for the CRC calculation, and the non-data information is generally sent to another functional block (such as a decoder or data processor) for subsequent processing. Since CRC block 60 performs a CRC calculation one word at a time, CRC block 60 generally requires at least N clock cycles to calculate CRC on data words Data0 12 through DataN 20.
Conventionally, the wider the bus(ses) and the greater the number of parallel data bits that can be processed simultaneously, the faster such data can be processed. Thus, CRC circuits have been developed to calculate a CRC on more than one word of data at a time (see, e.g., U.S. Patent Application Publication Nos. 2002/0053059 and 2002/0066059). However, since the data packet 10 can include any number of data words and/or data bits that conform to a conventional network data communications protocol, the “multiple data word” approach often results in the last word in data packet 10 having a length less than the full multiple word length.
FIG. 2A shows an example of a data packet 100, comprising a plurality of multiple word length data lines Data0 102 through DataN−1 108 and remainder line DataN 110. In this example, each of multiple word length data lines Data0 102 through DataN−1 108 has a length of 2m bits, where m>6. In a typical approach, m=7, and as a result, each of data lines Data0 102 through DataN−1 108 also has a length of four (4) words. However, remainder line DataN 110 may have a length of from 1 data bit to one bit less than the full multiple word length. In the typical “multiple word” data line approach where m=7, remainder line DataN 110 may have a length of from 1 to 3 data words. (Note that, in the case where m=7, remainder line DataN 110 cannot have a length of zero or four data words, although data packet 100 can contain 4*N or 4*(N−1) data words. In such cases, there simply is no remainder.)
Previous approaches to calculating a CRC on data units having a remainder line (i.e., where the packet contains a number of data bits that is not an integer multiple of the CRC calculating circuitry width) have resulted in architectures containing multiple sets of CRC hardware. One set of CRC hardware operated on the full length, multiple-word blocks or lines of data, and one or more other sets of CRC hardware operated on remainder data lines having a length less than the full, multiple-word length. In some cases, such as that shown in FIG. 2B, multiple CRC calculation circuit blocks 162, 164, 166, etc. are added to process remainders of variable lengths, in which the additional CRC calculation circuit blocks were configured to process data of different fixed lengths, and the appropriate individual CRC calculation circuit blocks of different fixed widths are selected to process data of a given length less than the full, multiple-word fixed length. The approach becomes more complicated as data processing widths increase.
An example of a simplified version of such a CRC architecture 150 is shown in FIG. 2B. Serial data is received by receiver 152 and is transferred to a logic/processing block 154 that detects and removes the header (and possibly other non-data information) from the data stream. (Other functional circuit blocks of architecture 150 are not shown for purposes of clarity in explaining the background.) The output of block 154 is input into a 1:m demultiplexer (or switch) 158, which selects one of outputs 161 . . . 163, 165 or 167 for processing by 2m bit-wide CRC calculator 160 . . . 4 bit CRC calculator 162, 2 bit CRC calculator 164, and 1 bit CRC calculator 166, respectively, depending on the state of control signal CONTROL. Depending on the value of m, additional CRC calculator blocks will be present to process data of successive power-of-2 bit lengths between 4 and 2m. The state of control signal CONTROL is determined by logic circuitry that detects the existence of remainder 110 and, optionally, determines the number of data bits in remainder 110. Most of the time, data lines 102-110 are received by demultiplexer 158, and control signal CONTROL selects bus 165 for transferring data lines 102-108 to 2m bit-wide CRC calculator 160, which can calculate a CRC on multiple data words in a single clock cycle. However, when remainder logic circuitry detects a remainder 110, control signal CONTROL changes state and selects one of busses 163, 165, 167 or a bus (not shown) between bus 163 and bus 161 for transferring all or part of data line 110 to data word CRC calculator 170, which is configured to calculate a CRC on one data word in one clock cycle. When remainder 110 contains a number of bits that is not a power of 2, it can take longer to calculate a CRC on remainder 110 than on a full-length, multiple-word data line.
While providing some improvement over the approach of FIGS. 1A-1B in calculation time, the approach of FIGS. 2A-2B is inefficient in terms of circuit use and/or chip area. A significant amount of chip real estate is dedicated to circuitry that is used infrequently or, in some cases, not at all (e.g., where a transmission protocol places restrictions on the number of words or bits in the data packet). Such architectures also unnecessarily consume power to keep all of the CRC circuitry active, even when it is not in use. In many cases, some bus lengths to and from second, third and/or further CRC blocks are relatively long, and thus consume incrementally greater power when transmitting data or even staying active, in comparison with the main (e.g., 2m bit) CRC block.
Needs therefore exist to maximize the operational efficiency and the functional circuit area efficiency of CRC circuitry and/or to further improve the CRC calculation speed, to keep up with ever-increasing demands for increased network speeds, smaller chip and board sizes and reduced power consumption.